adc.h
1.86 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
#ifndef ADC_H
#define ADC_H
#include "libwismart.h"
#include "ch.h"
#include "stm32f10x_gpio.h"
#include "stm32f10x_adc.h"
#define DBG(fmt,...) if(1){printf("[ADC] "fmt"\r\n", ##__VA_ARGS__);}else{({});}
#define ADCbatt_MIN_VALUE (0)
#define ADCbatt_MAX_VALUE (0xfff) /* 12-bit adc */
#define ADCbatt_VREF_PLUS (3300) /* Vref+ is connected with Vdda (3.3v) */
#define ADCbatt_VREF_MINUS (2300) /* Vref- is connected with Vssa (2.1v) */
#define ADCsound_MIN_VALUE (0)
#define ADCsound_MAX_VALUE (0xfff) /* 12-bit adc */
#define ADCsound_VREF_PLUS (2600) /* Vref+ is connected with Vdda (3.3v) */
#define ADCsound_VREF_MINUS (0) /* Vref- is connected with Vssa (0v) */
#define ADCbatt ADC1
#define ADCbatt_RCC RCC_APB2Periph_ADC1 /* */
#define ADCbatt_DIVIDER RCC_PCLK2_Div4 /* Can be 2/4/6/8. PCLK2 runs at 32Mhz, and max ADC clock is 14Mhz */
#define ADCbatt_CHANNEL ADC_Channel_12 /* 0/17 */
#define ADCbatt_SAMPLETIME ADC_SampleTime_239Cycles5
#define ADCbatt_GPIO_PIN GPIO_Pin_2
#define ADCbatt_GPIO_PORT GPIOC
#define ADCbatt_GPIO_RCC RCC_APB2Periph_GPIOC
#define ADCbatt_GPIO_STR "PC2"
#define ADCsound ADC2
#define ADCsound_RCC RCC_APB2Periph_ADC2 /* */
#define ADCsound_DIVIDER RCC_PCLK2_Div4 /* Can be 2/4/6/8. PCLK2 runs at 32Mhz, and max ADC clock is 14Mhz */
#define ADCsound_CHANNEL ADC_Channel_12 /* 0/17 */
#define ADCsound_SAMPLETIME ADC_SampleTime_239Cycles5
#define ADCsound_GPIO_PIN GPIO_Pin_2
#define ADCsound_GPIO_PORT GPIOA
#define ADCsound_GPIO_RCC RCC_APB2Periph_GPIOA
#define ADCsound_GPIO_STR "PA2"
void adc_batt_init(void);
uint32_t adc_batt_process(void);
uint16_t adc_batt_read(void);
void adc_batt_peripheralInit(void);
void adc_sound_init(void);
uint32_t adc_sound_process(void);
uint16_t adc_sound_read(void);
void adc_sound_peripheralInit(void);
#endif