/* ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, 2011,2012 Giovanni Di Sirio. This file is part of ChibiOS/RT. ChibiOS/RT is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. ChibiOS/RT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see . --- A special exception to the GPL can be applied should you wish to distribute a combined work that includes ChibiOS/RT, without being obliged to provide the source code for any proprietary components. See the file exception.txt for full details of how and when the exception can be applied. */ /** * @file STM32F4xx/stm32_rcc.h * @brief RCC helper driver header. * @note This file requires definitions from the ST header file * @p stm32f4xx.h. * * @addtogroup STM32F4xx_RCC * @{ */ #ifndef _STM32_RCC_ #define _STM32_RCC_ /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ /*===========================================================================*/ /* Driver macros. */ /*===========================================================================*/ /** * @name Generic RCC operations * @{ */ /** * @brief Enables the clock of one or more peripheral on the APB1 bus. * * @param[in] mask APB1 peripherals mask * @param[in] lp low power enable flag * * @api */ #define rccEnableAPB1(mask, lp) { \ RCC->APB1ENR |= (mask); \ if (lp) \ RCC->APB1LPENR |= (mask); \ } /** * @brief Disables the clock of one or more peripheral on the APB1 bus. * * @param[in] mask APB1 peripherals mask * @param[in] lp low power enable flag * * @api */ #define rccDisableAPB1(mask, lp) { \ RCC->APB1ENR &= ~(mask); \ if (lp) \ RCC->APB1LPENR &= ~(mask); \ } /** * @brief Resets one or more peripheral on the APB1 bus. * * @param[in] mask APB1 peripherals mask * * @api */ #define rccResetAPB1(mask) { \ RCC->APB1RSTR |= (mask); \ RCC->APB1RSTR = 0; \ } /** * @brief Enables the clock of one or more peripheral on the APB2 bus. * * @param[in] mask APB2 peripherals mask * @param[in] lp low power enable flag * * @api */ #define rccEnableAPB2(mask, lp) { \ RCC->APB2ENR |= (mask); \ if (lp) \ RCC->APB2LPENR |= (mask); \ } /** * @brief Disables the clock of one or more peripheral on the APB2 bus. * * @param[in] mask APB2 peripherals mask * @param[in] lp low power enable flag * * @api */ #define rccDisableAPB2(mask, lp) { \ RCC->APB2ENR &= ~(mask); \ if (lp) \ RCC->APB2LPENR &= ~(mask); \ } /** * @brief Resets one or more peripheral on the APB2 bus. * * @param[in] mask APB2 peripherals mask * * @api */ #define rccResetAPB2(mask) { \ RCC->APB2RSTR |= (mask); \ RCC->APB2RSTR = 0; \ } /** * @brief Enables the clock of one or more peripheral on the AHB1 bus. * * @param[in] mask AHB1 peripherals mask * @param[in] lp low power enable flag * * @api */ #define rccEnableAHB1(mask, lp) { \ RCC->AHB1ENR |= (mask); \ if (lp) \ RCC->AHB1LPENR |= (mask); \ } /** * @brief Disables the clock of one or more peripheral on the AHB1 bus. * * @param[in] mask AHB1 peripherals mask * @param[in] lp low power enable flag * * @api */ #define rccDisableAHB1(mask, lp) { \ RCC->AHB1ENR &= ~(mask); \ if (lp) \ RCC->AHB1LPENR &= ~(mask); \ } /** * @brief Resets one or more peripheral on the AHB1 bus. * * @param[in] mask AHB1 peripherals mask * * @api */ #define rccResetAHB1(mask) { \ RCC->AHB1RSTR |= (mask); \ RCC->AHB1RSTR = 0; \ } /** * @brief Enables the clock of one or more peripheral on the AHB2 bus. * * @param[in] mask AHB2 peripherals mask * @param[in] lp low power enable flag * * @api */ #define rccEnableAHB2(mask, lp) { \ RCC->AHB2ENR |= (mask); \ if (lp) \ RCC->AHB2LPENR |= (mask); \ } /** * @brief Disables the clock of one or more peripheral on the AHB2 bus. * * @param[in] mask AHB2 peripherals mask * @param[in] lp low power enable flag * * @api */ #define rccDisableAHB2(mask, lp) { \ RCC->AHB2ENR &= ~(mask); \ if (lp) \ RCC->AHB2LPENR &= ~(mask); \ } /** * @brief Resets one or more peripheral on the AHB2 bus. * * @param[in] mask AHB2 peripherals mask * * @api */ #define rccResetAHB2(mask) { \ RCC->AHB2RSTR |= (mask); \ RCC->AHB2RSTR = 0; \ } /** * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus. * * @param[in] mask AHB3 peripherals mask * @param[in] lp low power enable flag * * @api */ #define rccEnableAHB3(mask, lp) { \ RCC->AHB3ENR |= (mask); \ if (lp) \ RCC->AHB3LPENR |= (mask); \ } /** * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus. * * @param[in] mask AHB3 peripherals mask * @param[in] lp low power enable flag * * @api */ #define rccDisableAHB3(mask, lp) { \ RCC->AHB3ENR &= ~(mask); \ if (lp) \ RCC->AHB3LPENR &= ~(mask); \ } /** * @brief Resets one or more peripheral on the AHB3 (FSMC) bus. * * @param[in] mask AHB3 peripherals mask * * @api */ #define rccResetAHB3(mask) { \ RCC->AHB3RSTR |= (mask); \ RCC->AHB3RSTR = 0; \ } /** @} */ /** * @name ADC peripherals specific RCC operations * @{ */ /** * @brief Enables the ADC1 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) /** * @brief Disables the ADC1 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) /** * @brief Resets the ADC1 peripheral. * * @api */ #define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) /** * @brief Enables the ADC2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp) /** * @brief Disables the ADC2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp) /** * @brief Resets the ADC2 peripheral. * * @api */ #define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST) /** * @brief Enables the ADC3 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp) /** * @brief Disables the ADC3 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp) /** * @brief Resets the ADC3 peripheral. * * @api */ #define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST) /** @} */ /** * @name DMA peripheral specific RCC operations * @{ */ /** * @brief Enables the DMA1 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp) /** * @brief Disables the DMA1 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp) /** * @brief Resets the DMA1 peripheral. * * @api */ #define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST) /** * @brief Enables the DMA2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp) /** * @brief Disables the DMA2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp) /** * @brief Resets the DMA2 peripheral. * * @api */ #define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST) /** @} */ /** * @name PWR interface specific RCC operations * @{ */ /** * @brief Enables the PWR interface clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) /** * @brief Disables PWR interface clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) /** * @brief Resets the PWR interface. * * @api */ #define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) /** @} */ /** * @name CAN peripherals specific RCC operations * @{ */ /** * @brief Enables the CAN1 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) /** * @brief Disables the CAN1 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) /** * @brief Resets the CAN1 peripheral. * * @api */ #define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) /** * @brief Enables the CAN2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp) /** * @brief Disables the CAN2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp) /** * @brief Resets the CAN2 peripheral. * * @api */ #define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST) /** @} */ /** * @name ETH peripheral specific RCC operations * @{ */ /** * @brief Enables the ETH peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \ RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN, lp) /** * @brief Disables the ETH peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \ RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN, lp) /** * @brief Resets the ETH peripheral. * * @api */ #define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST) /** @} */ /** * @name I2C peripherals specific RCC operations * @{ */ /** * @brief Enables the I2C1 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) /** * @brief Disables the I2C1 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) /** * @brief Resets the I2C1 peripheral. * * @api */ #define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) /** * @brief Enables the I2C2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) /** * @brief Disables the I2C2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) /** * @brief Resets the I2C2 peripheral. * * @api */ #define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) /** * @brief Enables the I2C3 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp) /** * @brief Disables the I2C3 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp) /** * @brief Resets the I2C3 peripheral. * * @api */ #define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST) /** @} */ /** * @name OTG peripherals specific RCC operations * @{ */ /** * @brief Enables the OTG_FS peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp) /** * @brief Disables the OTG_FS peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp) /** * @brief Resets the OTG_FS peripheral. * * @api */ #define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST) /** @} */ /** * @name SDIO peripheral specific RCC operations * @{ */ /** * @brief Enables the SDIO peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccEnableSDIO(lp) rccEnableAPB2(RCC_APB2ENR_SDIOEN, lp) /** * @brief Disables the SDIO peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccDisableSDIO(lp) rccDisableAPB2(RCC_APB2ENR_SDIOEN, lp) /** * @brief Resets the SDIO peripheral. * @note Not supported in this family, does nothing. * * @api */ #define rccResetSDIO() rccResetAPB2(RCC_APB2RSTR_SDIORST) /** @} */ /** * @name SPI peripherals specific RCC operations * @{ */ /** * @brief Enables the SPI1 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) /** * @brief Disables the SPI1 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) /** * @brief Resets the SPI1 peripheral. * * @api */ #define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) /** * @brief Enables the SPI2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) /** * @brief Disables the SPI2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) /** * @brief Resets the SPI2 peripheral. * * @api */ #define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) /** * @brief Enables the SPI3 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) /** * @brief Disables the SPI3 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) /** * @brief Resets the SPI3 peripheral. * * @api */ #define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) /** @} */ /** * @name TIM peripherals specific RCC operations * @{ */ /** * @brief Enables the TIM1 peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) /** * @brief Disables the TIM1 peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) /** * @brief Resets the TIM1 peripheral. * * @api */ #define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) /** * @brief Enables the TIM2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) /** * @brief Disables the TIM2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) /** * @brief Resets the TIM2 peripheral. * * @api */ #define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) /** * @brief Enables the TIM3 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) /** * @brief Disables the TIM3 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) /** * @brief Resets the TIM3 peripheral. * * @api */ #define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) /** * @brief Enables the TIM4 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) /** * @brief Disables the TIM4 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) /** * @brief Resets the TIM4 peripheral. * * @api */ #define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) /** * @brief Enables the TIM5 peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) /** * @brief Disables the TIM5 peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) /** * @brief Resets the TIM5 peripheral. * * @api */ #define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) /** * @brief Enables the TIM8 peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) /** * @brief Disables the TIM8 peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) /** * @brief Resets the TIM8 peripheral. * * @api */ #define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) /** @} */ /** * @name USART/UART peripherals specific RCC operations * @{ */ /** * @brief Enables the USART1 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) /** * @brief Disables the USART1 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) /** * @brief Resets the USART1 peripheral. * * @api */ #define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) /** * @brief Enables the USART2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) /** * @brief Disables the USART2 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) /** * @brief Resets the USART2 peripheral. * * @api */ #define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) /** * @brief Enables the USART3 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) /** * @brief Disables the USART3 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) /** * @brief Resets the USART3 peripheral. * * @api */ #define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) /** * @brief Enables the USART6 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp) /** * @brief Disables the USART6 peripheral clock. * * @param[in] lp low power enable flag * * @api */ #define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp) /** * @brief Enables the UART4 peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) /** * @brief Disables the UART4 peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) /** * @brief Resets the UART4 peripheral. * * @api */ #define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) /** * @brief Enables the UART5 peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) /** * @brief Disables the UART5 peripheral clock. * @note The @p lp parameter is ignored in this family. * * @param[in] lp low power enable flag * * @api */ #define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) /** * @brief Resets the UART5 peripheral. * * @api */ #define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) /** * @brief Resets the USART6 peripheral. * * @api */ #define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST) /** @} */ /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ #ifdef __cplusplus extern "C" { #endif #ifdef __cplusplus } #endif #endif /* _STM32_RCC_ */ /** @} */