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/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @defgroup STM32F1xx_DRIVERS STM32F1xx Drivers
* @details This section describes all the supported drivers on the STM32F1xx
* platform and the implementation details of the single drivers.
*
* @ingroup platforms
*/
/**
* @defgroup STM32F1xx_HAL STM32F1xx Initialization Support
* @details The STM32F1xx HAL support is responsible for system initialization.
*
* @section stm32f1xx_hal_1 Supported HW resources
* - PLL1.
* - PLL2 (where present).
* - RCC.
* - Flash.
* .
* @section stm32f1xx_hal_2 STM32F1xx HAL driver implementation features
* - PLLs startup and stabilization.
* - Clock tree initialization.
* - Clock source selection.
* - Flash wait states initialization based on the selected clock options.
* - SYSTICK initialization based on current clock and kernel required rate.
* - DMA support initialization.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_ADC STM32F1xx ADC Support
* @details The STM32F1xx ADC driver supports the ADC peripherals using DMA
* channels for maximum performance.
*
* @section stm32f1xx_adc_1 Supported HW resources
* - ADC1.
* - DMA1.
* .
* @section stm32f1xx_adc_2 STM32F1xx ADC driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Streaming conversion using DMA for maximum performance.
* - Programmable ADC interrupt priority level.
* - Programmable DMA bus priority for each DMA channel.
* - Programmable DMA interrupt priority for each DMA channel.
* - DMA errors detection.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_CAN STM32F1xx CAN Support
* @details The STM32F1xx CAN driver uses the CAN peripherals.
*
* @section stm32f1xx_can_1 Supported HW resources
* - bxCAN1.
* .
* @section stm32f1xx_can_2 STM32F1xx CAN driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Support for bxCAN sleep mode.
* - Programmable bxCAN interrupts priority level.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_EXT STM32F1xx EXT Support
* @details The STM32F1xx EXT driver uses the EXTI peripheral.
*
* @section stm32f1xx_ext_1 Supported HW resources
* - EXTI.
* .
* @section stm32f1xx_ext_2 STM32F1xx EXT driver implementation features
* - Each EXTI channel can be independently enabled and programmed.
* - Programmable EXTI interrupts priority level.
* - Capability to work as event sources (WFE) rather than interrupt sources.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_GPT STM32F1xx GPT Support
* @details The STM32F1xx GPT driver uses the TIMx peripherals.
*
* @section stm32f1xx_gpt_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* - TIM4.
* - TIM5.
* .
* @section stm32f1xx_gpt_2 STM32F1xx GPT driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable TIMx interrupts priority level.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_I2C STM32F1xx I2C Support
* @details The STM32F1xx I2C driver uses the I2Cx peripherals.
*
* @section stm32f1xx_i2c_1 Supported HW resources
* - I2C1.
* - I2C2.
* .
* @section stm32f1xx_i2c_2 STM32F1xx I2C driver implementation features
* - Each I2C port can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable I2Cx interrupts priority level.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_ICU STM32F1xx ICU Support
* @details The STM32F1xx ICU driver uses the TIMx peripherals.
*
* @section stm32f1xx_icu_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* - TIM4.
* - TIM5.
* .
* @section stm32f1xx_icu_2 STM32F1xx ICU driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable TIMx interrupts priority level.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_MAC STM32F1xx MAC Support
* @details The STM32 MAC driver supports the ETH peripheral.
*
* @section at91sam7_mac_1 Supported HW resources
* - ETH.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_PAL STM32F1xx PAL Support
* @details The STM32F1xx PAL driver uses the GPIO peripherals.
*
* @section stm32f1xx_pal_1 Supported HW resources
* - AFIO.
* - GPIOA.
* - GPIOB.
* - GPIOC.
* - GPIOD.
* - GPIOE (where present).
* - GPIOF (where present).
* - GPIOG (where present).
* .
* @section stm32f1xx_pal_2 STM32F1xx PAL driver implementation features
* The PAL driver implementation fully supports the following hardware
* capabilities:
* - 16 bits wide ports.
* - Atomic set/reset functions.
* - Atomic set+reset function (atomic bus operations).
* - Output latched regardless of the pad setting.
* - Direct read of input pads regardless of the pad setting.
* .
* @section stm32f1xx_pal_3 Supported PAL setup modes
* The STM32F1xx PAL driver supports the following I/O modes:
* - @p PAL_MODE_RESET.
* - @p PAL_MODE_UNCONNECTED.
* - @p PAL_MODE_INPUT.
* - @p PAL_MODE_INPUT_PULLUP.
* - @p PAL_MODE_INPUT_PULLDOWN.
* - @p PAL_MODE_INPUT_ANALOG.
* - @p PAL_MODE_OUTPUT_PUSHPULL.
* - @p PAL_MODE_OUTPUT_OPENDRAIN.
* - @p PAL_MODE_STM32F1xx_ALTERNATE_PUSHPULL (non standard).
* - @p PAL_MODE_STM32F1xx_ALTERNATE_OPENDRAIN (non standard).
* .
* Any attempt to setup an invalid mode is ignored.
*
* @section stm32f1xx_pal_4 Suboptimal behavior
* The STM32F1xx GPIO is less than optimal in several areas, the limitations
* should be taken in account while using the PAL driver:
* - Pad/port toggling operations are not atomic.
* - Pad/group mode setup is not atomic.
* - Writing on pads/groups/ports programmed as input with pull-up/down
* resistor can change the resistor setting because the output latch is
* used for resistor selection.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_PWM STM32F1xx PWM Support
* @details The STM32F1xx PWM driver uses the TIMx peripherals.
*
* @section stm32f1xx_pwm_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* - TIM4.
* - TIM5.
* .
* @section stm32f1xx_pwm_2 STM32F1xx PWM driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Four independent PWM channels per timer.
* - Programmable TIMx interrupts priority level.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_RTC STM32F1xx RTC Support
* @details The STM32F1xx RTC driver uses the RTC peripheral.
*
* @section stm32f1xx_rtc_1 Supported HW resources
* - RTC.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_SDC STM32F1xx SDC Support
* @details The STM32F1xx SDC driver uses the SDIO peripheral.
*
* @section stm32f1xx_sdc_1 Supported HW resources
* - SDIO.
* - DMA2.
* .
* @section stm32f1xx_sdc_2 STM32F1xx SDC driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Programmable interrupt priority.
* - DMA is used for receiving and transmitting.
* - Programmable DMA bus priority for each DMA channel.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_SERIAL STM32F1xx Serial Support
* @details The STM32F1xx Serial driver uses the USART/UART peripherals in a
* buffered, interrupt driven, implementation.
*
* @section stm32f1xx_serial_1 Supported HW resources
* The serial driver can support any of the following hardware resources:
* - USART1.
* - USART2.
* - USART3 (where present).
* - UART4 (where present).
* - UART5 (where present).
* .
* @section stm32f1xx_serial_2 STM32F1xx Serial driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each UART/USART can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Fully interrupt driven.
* - Programmable priority levels for each UART/USART.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_SPI STM32F1xx SPI Support
* @details The SPI driver supports the STM32F1xx SPI peripherals using DMA
* channels for maximum performance.
*
* @section stm32f1xx_spi_1 Supported HW resources
* - SPI1.
* - SPI2.
* - SPI3 (where present).
* - DMA1.
* - DMA2 (where present).
* .
* @section stm32f1xx_spi_2 STM32F1xx SPI driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each SPI can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable interrupt priority levels for each SPI.
* - DMA is used for receiving and transmitting.
* - Programmable DMA bus priority for each DMA channel.
* - Programmable DMA interrupt priority for each DMA channel.
* - Programmable DMA error hook.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_UART STM32F1xx UART Support
* @details The UART driver supports the STM32F1xx USART peripherals using DMA
* channels for maximum performance.
*
* @section stm32f1xx_uart_1 Supported HW resources
* The UART driver can support any of the following hardware resources:
* - USART1.
* - USART2.
* - USART3 (where present).
* - UART4 (where present).
* - DMA1.
* - DMA2 (where present).
* .
* @section stm32f1xx_uart_2 STM32F1xx UART driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each UART/USART can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable interrupt priority levels for each UART/USART.
* - DMA is used for receiving and transmitting.
* - Programmable DMA bus priority for each DMA channel.
* - Programmable DMA interrupt priority for each DMA channel.
* - Programmable DMA error hook.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_USB STM32F1xx USB Support
* @details The USB driver supports the STM32F1xx USB peripheral.
*
* @section stm32f1xx_usb_1 Supported HW resources
* The USB driver can support any of the following hardware resources:
* - USB.
* .
* @section stm32f1xx_usb_2 STM32F1xx USB driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Programmable interrupt priority levels.
* - Each endpoint programmable in Control, Bulk and Interrupt modes.
* .
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_PLATFORM_DRIVERS STM32F1xx Platform Drivers
* @details Platform support drivers. Platform drivers do not implement HAL
* standard driver templates, their role is to support platform
* specific functionalities.
*
* @ingroup STM32F1xx_DRIVERS
*/
/**
* @defgroup STM32F1xx_DMA STM32F1xx DMA Support
* @details This DMA helper driver is used by the other drivers in order to
* access the shared DMA resources in a consistent way.
*
* @section stm32f1xx_dma_1 Supported HW resources
* The DMA driver can support any of the following hardware resources:
* - DMA1.
* - DMA2 (where present).
* .
* @section stm32f1xx_dma_2 STM32F1xx DMA driver implementation features
* - Exports helper functions/macros to the other drivers that share the
* DMA resource.
* - Automatic DMA clock stop when not in use by any driver.
* - DMA streams and interrupt vectors sharing among multiple drivers.
* .
* @ingroup STM32F1xx_PLATFORM_DRIVERS
*/
/**
* @defgroup STM32F1xx_RCC STM32F1xx RCC Support
* @details This RCC helper driver is used by the other drivers in order to
* access the shared RCC resources in a consistent way.
*
* @section stm32f1xx_rcc_1 Supported HW resources
* - RCC.
* .
* @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features
* - Peripherals reset.
* - Peripherals clock enable.
* - Peripherals clock disable.
* .
* @ingroup STM32F1xx_PLATFORM_DRIVERS
*/
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